As the technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. In one process of forming a metal gate structure, known as “gate last” process, the final gate structure is fabricated “last,” which allows reduced number of subsequent processes, including high temperature processing that must be performed after formation of the gate.
Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high-dielectric-constant (high-k) gate dielectric layers are also used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a thinner layer of the gate oxide used in larger technology nodes.
However, there are challenges to implementing such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, in a “high-k last” fabrication process in which the final high dielectric constant (high-k) dielectric is fabricated last in a “gate last” process, an outer edge of a lightly doped source/drain (LDD) region may be offset from an outer edge of a metal gate electrode.
FIG. 1 shows a cross-sectional view of a semiconductor device 100 fabricated by a “high-k last” process with a conventional gate structure 142. The semiconductor device 100 can be formed over an active region 104 of a substrate 102 adjacent to isolation regions 106. The semiconductor device 100 comprises lightly doped source/drain (LDD) regions 122 and source/drain (S/D) regions 124 formed in the active region 104 of the substrate 102, a gate structure 142 comprising an interfacial layer 143, a gate dielectric layer 144 and a gate electrode 146 sequentially formed over the substrate 102. Additionally, gate spacers 132, contact etch stop layers (CESL) 134 and interlayer dielectric (ILD) layers 136 may surround the gate structure 142.
Due to the “high-k last” process, an outer edge 122e of the LDD region 122 is often offset a distance X from an outer edge 146e of the gate electrode 146. Such an offset could be of a distance enough to degrade device performance if its formation is not prevented. Accordingly, what is needed is an improved device and method of gate formation.